1. Field of the Invention
This invention relates generally to the field of electronic circuit design and more particularly relates to a semiconductor platform having a configurable power mesh for multiple frequency and power requirements on a semiconductor product.
2. Description of Related Art
Integrated circuits and chips have become increasingly complex and the speed and capacity of chips doubles about every eighteen months because of advances in design software, fabrication technology, semiconductor materials, and chip design. The increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to specify and design a chip that performs as actually specified. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures often adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application; yet the demand for complex custom-designed chips increases with the burgeoning number and variety of microprocessor-driven applications and products. The time and money required to design chips have become a bottleneck to bring these new semiconductor products to market. Without an assured successful outcome that the semiconductor product will be designed within a specified time and will perform as designed, the risks have risen along with costs and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
What makes integrated circuits so expensive requiring intensive effort is that they are comprised of millions of transistors and the electrical interconnections between them. Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty to design a high speed integrated circuit. An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers is determined by the concentration of dopants within the area. In turn, these distinct areas interact with one another to form transistors, diodes, and other electronic devices. These specific transistors and other devices may interact with each other by field interactions or by direct electrical interconnections. Openings or windows are created for electrical connections between the layers by a combination of masking, layering, and etching additional materials on top of the wafers. Electrical interconnections may be within the semiconductor or may lie above the semiconductor areas in layers of a complex mesh of conductive power, ground, and signal lines, usually of material such as platinum, gold, aluminum, tungsten, or copper metal. Depending upon the interconnection topology, also very complex, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. Insulative layers, e.g., silicon dioxide, may separate any of these semiconductor or connectivity layers. A power distribution network of power, ground, and signal lines in a multilayered grid typically spans the entire die or a large functional unit in each metallization layer and is horizontally related to decoupling capacitors diffused in the base wafer. The power and ground lines typically alternate in the layers and the power/ground/signal straps are typically orthogonal to the power/ground/signal straps in the layers above and/or below it. Vias connect a power (ground) line or strap to another power (ground) line/strap at the overlap sites. Signal lines typically surround the power/ground straps. To facilitate higher operating frequencies on the integrated circuits, additional decoupling capacitors were typically diffused in the base layer and, up till now, the power mesh was fixed in the layers above the capacitors with a fixed number of horizontal and vertical straps in the layers.
Meanwhile, integrated circuit design has developed a modular approach in which the areas or blocks of transistors and their respective functions are fixed and other areas in which the transistors and their functions are totally or partially programmable and/or customizable. The proportion of fixed-to-programmable modules in an integrated circuit is determined by the complexity, cost, time, and design constraints. The programmable modules or entire integrated circuits may be made up of a field programmable gate array (FPGA) that is a logic chip that can be reprogrammed to obtain different functions. FPGAs are used primarily for prototyping integrated circuit designs but once the designs are set, faster hard-wired chips are produced. On one hand, although the gate arrays are programmable making the FPGAs flexible and modification trivial, the power mesh of FPGAs is fixed in the lower levels. In addition, FPGAs are very expensive and have the largest die size. FPGAs, thus, have a high cost per function, low speed, and high power consumption. Programmable gate arrays (PGAs) are also flexible in the number of possible applications that can be achieved but are not quite as flexible as the FPGAs and are more time-consuming to modify and test. An application-specific integrated circuit (ASIC) is another type of chip designed for a particular application. ASICs are efficient in use of power compared to FPGAs and are quite inexpensive to manufacture at high volumes. ASICs, however, are very complex to design and prototype because of their speed and quality. Application Specific Standard Products (ASSPs) are hard-wired chips that meet a specific need but this customization is both time-consuming and costly. An example of an ASSP might be a microprocessor in a heart pacemaker.
In the industry, a new paradigm for the design of semiconductor products has emerged; one company may develop the register transfer logic (RTL) of a semiconductor platform having embedded elements and programmable elements. The RTL of the semiconductor platform is then given to a chip designer in the same or another company who incorporates other embedded elements and programs the remaining platform into a specific semiconductor product. The platform may have embedded elements diffused into the semiconductor wafer that may function at higher frequencies than other embedded elements. Examples of those blocks or elements operating at higher frequencies may be input/output communication devices and/or processors operating in the range of gigahertz frequencies. The programmable elements typically comprise a “sea” or “fabric” of transistors that can be logically configured and interconnected among each other and among the metal layers to achieve a specific application. The transistor fabric and the power grid/decoupling capacitors are typically predesigned to operate at an expected maximum frequency and switching limits (currently about 166 MHz) for the custom logic they are expected to support. Thus, even though the transistors may switch at higher frequencies, the collateral power grid and decoupling capacitors do not support these higher frequency functions because the increased high frequency harmonics result in increased noise. A shortcoming of this model of readily-available platforms is that transistor fabric is offered in a “one size fits all” configuration. Whether the fabric is adjacent to a high-speed input/output communication port on the chip or in the interior of the chip where potentially lower-speed state machines might be instantiated, the same frequency and power limits exist because the fabric is homogeneous. High speed communications, moreover, have many variations; each variation requiring different components in the integrated circuit associated with its communications protocol.
In order to function in the realm of higher frequencies, a denser grid of power and ground lines and more decoupling capacitors are required to manage the higher power dissipation, inductance, and other electrical characteristics, but in the present technology the number of and the placement of decoupling capacitors and the power grid itself has been fixed and cannot accommodate the demand for higher performance. Increasing the capability of the underlying grid may enable higher frequencies but reduces the density of the support transistor fabric while increases the routing difficulty. Merely “beefing up” the grid worsens the economics of the platform. Careful layout and review of those areas of design are also possible, allowing the frequency limits to be exceeded in small constrained areas of the design, but this approach may not work for all designs and, more importantly, it is extremely time-consuming demanding intensive engineering. Finally, designs requiring higher frequency operation can be “widened” which means increasing the number of data paths by two or more, and decreasing the operating frequency in order to maintain bandwidth. Increasing bus widths in order to limit frequency requirements is workable but that approach increases the latency for data passing through the system. Increasing the bus size by two or more increases routing complexity by much more. Thus, there is an inevitable compromise between high frequency and power requirements.
The semiconductor platform may include an electrical and mechanical transceiver hardware, called a PHY, embedded in the platform for high speed digital and/or optical communication. The PHY hardware typically amplifies, modulates, shapes the waveforms, transmits, and receives the electrical impulses, light or radio signals of the data. The PHY also encodes and decodes the data stream to and from the upper protocols, serializes coded groups into bit streams and then deserializes the receiving bit streams into code groups. An example of one kind of PHY embodies full duplex, point-to-point communications channel for gigabit speed serial interfaces that is independent of the communication protocol and may be independent of the media. Another type of PHY may be an optoelectronic interconnect for broadband and networking applications for extremely high bandwidth CMOS ASICs. Some communication protocols, such as Ethernet, Fibre Channel, SONET/SDH, Serial ATA, and ATM, require specialized PHY layers. The PHY is connected to the next protocol, the data link protocol, in which data packets are encoded and decoded into bits. The data link layer, with knowledge of the transmission protocol, manages errors in the PHY, flow control, and frame synchronization.
Not only do digital communications among networks require high speed interfaces and processing, processing functions on the chip process are faster and faster. The fastest computer now processes on the order of 36 trillion operations per second. These fast processors require fast registers, fast memories called caches, and fast busses that move data in and out of the processors and memory. Processor architecture is a complete science onto itself and is as complex or more so than high-speed communications which may be encompassed within the processing and data availability requirements. Simply put, everything is faster today—from the processors, the registers, the caches, the communications buses, the protocols, the PHYs—at least one section of an integrated circuit today is dedicated to high speed operations.
Because there are so many variations in the applications, the data, the speeds, and standards, it is very expensive and burdensome to design and manufacture individual full custom chips for specific applications, specific processors, and protocols. Thus, there is a need in the industry to accommodate desired flexibility and variety available in high speed digital processing, communication, and information handling systems. In addition, developers need off-the-shelf building blocks to design these multisystem solutions to save time and engineering resources.
There is an additional need in the industry to offer flexibility to implement high-speed data processing and/or communications in specific areas of an integrated circuit in order to minimize power and complexity.